Jr. FPGA Design/Verification Engineer (Location: Hyderabad)

Job Responsibilities:

  • Should have at least 6 months to 1 year exp, in FPGA RTL (mostly verilog) design, architect understanding debugging and synthesis exp
  • Exp. In Xilinx/ISE latest version is a must.
  • Should be a good team player, able to work smoothly with the other team member
  • Should be prepared to work with h/w board level design and board bring up team (in case needed).
  • Having some basic knowledge on h/w such as : ADC, DAC, basic digital design ICs, micro-controller and USB/UART/SPI i/f and memory devices.
  • Candidates should have ECE, Electronics or VLSI design in their curriculum & after their graduation/PG need to have undergone yr. course on FPGA/VLSI.



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